Circuit designs to be implemented within integrated circuit devices (ICs) are typically expressed in programmatic form. For example, a circuit design can be expressed as a netlist, as one or more hardware description language files, or the like. The circuit design can specify, or include, a plurality of input/output (I/O) pins in conjunction with logic and other circuit structures. Each I/O pin references a node within the circuit design that will either send a signal from the IC to a destination external to the IC or receive a signal into the IC from a source that is external to the IC.
In order to communicate signals to or from the IC, each I/O pin must be assigned, or mapped, to a physical pin on the packaging of the IC. Physical pins on the packaging of the IC, also referred to as package pins, typically are grouped into one or more banks. Once an I/O pin is mapped or assigned to a particular package pin, the I/O pin can be routed or connected to the assigned package pin.
I/O pins can be mapped to package pins through a manual process or through an automated process. Modern ICs, including programmable logic devices (PLDs), can include a significant number of package pins. A field programmable gate array type of PLD, for example, can include hundreds of package pins. In light of the size and complexity of modern ICs, it can be appreciated that manually mapping I/O pins to package pins can be a difficult and tedious process. This is particularly true as various constraints must be observed. For example, it is usually the case that each bank of package pins of the IC may include only I/O pins of a same I/O standard.
Automated mapping of I/O pins to package pins can be performed by an electronic design automation (EDA) tool. An EDA tool can determine a placement for the I/O pins that will conform to established constraints, e.g., that the package pins of a same bank may only be assigned to I/O pins of a same I/O standard. Automated mapping techniques, however, disregard aspects of system design that are external to the IC itself. For example, while an automatic pin placement technique will ensure that I/O standard constraints are observed, the technique will not take into consideration circuit board layout or any other factors unrelated to the internal workings and architecture of the IC when mapping I/O pins to package pins.